5th IEEE International Conference on Electronics, Circuits
and Systems
Lisbon, September 7 to 10, 1998
A Single-Piece Charge-Based Model for the Output Conductance of MOS
Transistors
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Márcio C. Schneider
Universidade Federal de Santa Catarina - Departamento de Engenharia
Elétrica
Caixa Postal 5119 - CEP 88040-970 Florianópolis, Santa Catarina,
Brasil
E-Mail: marcio@eel.ufsc.br
Carlos Galup-Montoro
Universidade Federal de Santa Catarina - Departamento de Engenharia
Elétrica
Caixa Postal 5119 - CEP 88040-970 Florianópolis, Santa Catarina,
Brasil
E-Mail: carlos@eel.ufsc.br
Oscar C. Gouveia Filho
Universidade Federal do Paraná - Departamento de Engenharia
Elétrica
Caixa Postal 19011 - CEP 81531-970 Curitiba, Paraná, Brasil
E-mail: ogouveia@eletr.ufpr.br
Ana Isabela A. Cunha
Universidade Federal da Bahia - Departamento de Engenharia Elétrica
E-mail: aiac@ufba.br
Abstract
This paper presents a physically based model of the MOSFET output conductance.
The drain current and the output conductance of the MOS transistor are
accurately described by single-piece functionsof the inversion charge densities
at source and drain. Carrier velocity saturation, channel length modulation
(CLM) and drain induced barrier lowering (DIBL) are included in a single-piece
analytical model. The results herein can be readily applied for first order
analog circuit hand calculation.